 
cpldfit:  version M.53d                             Xilinx Inc.
                                  Fitter Report
Design Name: MSX_SRAM_mapper_512K                Date: 12- 9-2010,  8:16AM
Device Used: XC9536-7-VQ44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
35 /36  ( 97%) 110 /180  ( 61%) 69 /72  ( 96%)   20 /36  ( 56%) 24 /34  ( 71%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          17/18       36/36*      36          56/90      11/17
FB2          18/18*      33/36       33          54/90       0/17
             -----       -----                   -----       -----     
             35/36       69/72                  110/180     11/34 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   13          13    |  I/O              :    24      28
Output        :    6           6    |  GCK/IO           :     0       3
Bidirectional :    5           5    |  GTS/IO           :     0       2
GCK           :    0           0    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     24          24

** Power Data **

There are 0 macrocells in high performance mode (MCHP).
There are 35 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'MSX_SRAM_mapper_512K.ise'.
*************************  Summary of Mapped Logic  ************************

** 11 Outputs **

Signal                Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                  Pts   Inps          No.  Type    Use     Mode Rate State
ma14                  4     6     FB1_1   40   I/O     O       LOW  FAST 
ma15                  4     6     FB1_2   41   I/O     O       LOW  FAST 
ma16                  4     6     FB1_4   42   I/O     O       LOW  FAST 
ma17                  4     6     FB1_6   2    I/O     O       LOW  FAST 
ma18                  4     6     FB1_8   3    I/O     O       LOW  FAST 
Busdir                1     8     FB1_9   5    I/O     O       LOW  FAST 
d4                    5     14    FB1_13  12   I/O     I/O     LOW  FAST 
d3                    5     14    FB1_14  13   I/O     I/O     LOW  FAST 
d2                    5     14    FB1_15  14   I/O     I/O     LOW  FAST 
d1                    5     14    FB1_16  16   I/O     I/O     LOW  FAST 
d0                    5     14    FB1_17  18   I/O     I/O     LOW  FAST 

** 24 Buried Nodes **

Signal                Total Total Loc     Pwr  Reg Init
Name                  Pts   Inps          Mode State
ff_bit4/ff_bit4_CLKF  1     4     FB1_5   LOW  
fe_bit4/fe_bit4_CLKF  1     4     FB1_7   LOW  
fd_bit4/fd_bit4_CLKF  1     4     FB1_10  LOW  
fc_bit4/fc_bit4_CLKF  1     4     FB1_11  LOW  
ff_bit4               3     9     FB1_12  LOW  RESET
ff_bit3               3     9     FB1_18  LOW  RESET
ff_bit2               3     9     FB2_1   LOW  RESET
ff_bit1               3     9     FB2_2   LOW  RESET
ff_bit0               3     9     FB2_3   LOW  RESET
fe_bit4               3     9     FB2_4   LOW  RESET
fe_bit3               3     9     FB2_5   LOW  RESET
fe_bit2               3     9     FB2_6   LOW  RESET
fe_bit1               3     9     FB2_7   LOW  RESET
fe_bit0               3     9     FB2_8   LOW  SET
fd_bit4               3     9     FB2_9   LOW  RESET
fd_bit3               3     9     FB2_10  LOW  RESET
fd_bit2               3     9     FB2_11  LOW  RESET
fd_bit1               3     9     FB2_12  LOW  SET
fd_bit0               3     9     FB2_13  LOW  RESET
fc_bit4               3     9     FB2_14  LOW  RESET
fc_bit3               3     9     FB2_15  LOW  RESET
fc_bit2               3     9     FB2_16  LOW  RESET
fc_bit1               3     9     FB2_17  LOW  SET
fc_bit0               3     9     FB2_18  LOW  SET

** 13 Inputs **

Signal                Loc     Pin  Pin     Pin     
Name                          No.  Type    Use     
a14                   FB1_10  6    I/O     I
a15                   FB1_11  7    I/O     I
RD                    FB1_12  8    I/O     I
WR                    FB2_1   39   I/O     I
a7                    FB2_2   38   I/O     I
a6                    FB2_4   37   I/O     I
a5                    FB2_7   32   I/O     I
a4                    FB2_10  29   I/O     I
a3                    FB2_12  27   I/O     I
a2                    FB2_13  23   I/O     I
a1                    FB2_14  22   I/O     I
a0                    FB2_15  21   I/O     I
IORQ                  FB2_16  20   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               36/0
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ma14                  4       0     0   1     FB1_1   40    I/O     O
ma15                  4       0     0   1     FB1_2   41    I/O     O
(unused)              0       0     0   5     FB1_3   43    GCK/I/O 
ma16                  4       0     0   1     FB1_4   42    I/O     O
ff_bit4/ff_bit4_CLKF
                      1       0     0   4     FB1_5   44    GCK/I/O (b)
ma17                  4       0     0   1     FB1_6   2     I/O     O
fe_bit4/fe_bit4_CLKF
                      1       0     0   4     FB1_7   1     GCK/I/O (b)
ma18                  4       0     0   1     FB1_8   3     I/O     O
Busdir                1       0     0   4     FB1_9   5     I/O     O
fd_bit4/fd_bit4_CLKF
                      1       0     0   4     FB1_10  6     I/O     I
fc_bit4/fc_bit4_CLKF
                      1       0     0   4     FB1_11  7     I/O     I
ff_bit4               3       0     0   2     FB1_12  8     I/O     I
d4                    5       0     0   0     FB1_13  12    I/O     I/O
d3                    5       0     0   0     FB1_14  13    I/O     I/O
d2                    5       0     0   0     FB1_15  14    I/O     I/O
d1                    5       0     0   0     FB1_16  16    I/O     I/O
d0                    5       0     0   0     FB1_17  18    I/O     I/O
ff_bit3               3       0     0   2     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: IORQ              13: a5                25: fd_bit4 
  2: d3.PIN            14: a6                26: fe_bit0 
  3: d4.PIN            15: a7                27: fe_bit1 
  4: RD                16: fc_bit0           28: fe_bit2 
  5: WR                17: fc_bit1           29: fe_bit3 
  6: a0                18: fc_bit2           30: fe_bit4 
  7: a14               19: fc_bit3           31: ff_bit0 
  8: a15               20: fc_bit4           32: ff_bit1 
  9: a1                21: fd_bit0           33: ff_bit2 
 10: a2                22: fd_bit1           34: ff_bit3 
 11: a3                23: fd_bit2           35: ff_bit4 
 12: a4                24: fd_bit3           36: ff_bit4/ff_bit4_CLKF 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ma14                 ......XX.......X....X....X....X......... 6       6
ma15                 ......XX........X....X....X....X........ 6       6
ma16                 ......XX.........X....X....X....X....... 6       6
ff_bit4/ff_bit4_CLKF 
                     X...XX..X............................... 4       4
ma17                 ......XX..........X....X....X....X...... 6       6
fe_bit4/fe_bit4_CLKF 
                     X...XX..X............................... 4       4
ma18                 ......XX...........X....X....X....X..... 6       6
Busdir               X..X.....XXXXXX......................... 8       8
fd_bit4/fd_bit4_CLKF 
                     X...XX..X............................... 4       4
fc_bit4/fc_bit4_CLKF 
                     X...XX..X............................... 4       4
ff_bit4              ..X......XXXXXX...................XX.... 9       9
d4                   X..X.X..XXXXXXX....X....X....X....X..... 14      14
d3                   X..X.X..XXXXXXX...X....X....X....X...... 14      14
d2                   X..X.X..XXXXXXX..X....X....X....X....... 14      14
d1                   X..X.X..XXXXXXX.X....X....X....X........ 14      14
d0                   X..X.X..XXXXXXXX....X....X....X......... 14      14
ff_bit3              .X.......XXXXXX..................X.X.... 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               33/3
Number of signals used by logic mapping into function block:  33
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ff_bit2               3       0     0   2     FB2_1   39    I/O     I
ff_bit1               3       0     0   2     FB2_2   38    I/O     I
ff_bit0               3       0     0   2     FB2_3   36    GTS/I/O (b)
fe_bit4               3       0     0   2     FB2_4   37    I/O     I
fe_bit3               3       0     0   2     FB2_5   34    GTS/I/O (b)
fe_bit2               3       0     0   2     FB2_6   33    GSR/I/O (b)
fe_bit1               3       0     0   2     FB2_7   32    I/O     I
fe_bit0               3       0     0   2     FB2_8   31    I/O     (b)
fd_bit4               3       0     0   2     FB2_9   30    I/O     (b)
fd_bit3               3       0     0   2     FB2_10  29    I/O     I
fd_bit2               3       0     0   2     FB2_11  28    I/O     (b)
fd_bit1               3       0     0   2     FB2_12  27    I/O     I
fd_bit0               3       0     0   2     FB2_13  23    I/O     I
fc_bit4               3       0     0   2     FB2_14  22    I/O     I
fc_bit3               3       0     0   2     FB2_15  21    I/O     I
fc_bit2               3       0     0   2     FB2_16  20    I/O     I
fc_bit1               3       0     0   2     FB2_17  19    I/O     (b)
fc_bit0               3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d0.PIN            12: fc_bit0               23: fd_bit4/fd_bit4_CLKF 
  2: d1.PIN            13: fc_bit1               24: fe_bit0 
  3: d2.PIN            14: fc_bit2               25: fe_bit1 
  4: d3.PIN            15: fc_bit3               26: fe_bit2 
  5: d4.PIN            16: fc_bit4               27: fe_bit3 
  6: a2                17: fc_bit4/fc_bit4_CLKF  28: fe_bit4 
  7: a3                18: fd_bit0               29: fe_bit4/fe_bit4_CLKF 
  8: a4                19: fd_bit1               30: ff_bit0 
  9: a5                20: fd_bit2               31: ff_bit1 
 10: a6                21: fd_bit3               32: ff_bit2 
 11: a7                22: fd_bit4               33: ff_bit4/ff_bit4_CLKF 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
ff_bit2              ..X..XXXXXX....................XX....... 9       9
ff_bit1              .X...XXXXXX...................X.X....... 9       9
ff_bit0              X....XXXXXX..................X..X....... 9       9
fe_bit4              ....XXXXXXX................XX........... 9       9
fe_bit3              ...X.XXXXXX...............X.X........... 9       9
fe_bit2              ..X..XXXXXX..............X..X........... 9       9
fe_bit1              .X...XXXXXX.............X...X........... 9       9
fe_bit0              X....XXXXXX............X....X........... 9       9
fd_bit4              ....XXXXXXX..........XX................. 9       9
fd_bit3              ...X.XXXXXX.........X.X................. 9       9
fd_bit2              ..X..XXXXXX........X..X................. 9       9
fd_bit1              .X...XXXXXX.......X...X................. 9       9
fd_bit0              X....XXXXXX......X....X................. 9       9
fc_bit4              ....XXXXXXX....XX....................... 9       9
fc_bit3              ...X.XXXXXX...X.X....................... 9       9
fc_bit2              ..X..XXXXXX..X..X....................... 9       9
fc_bit1              .X...XXXXXX.X...X....................... 9       9
fc_bit0              X....XXXXXXX....X....................... 9       9
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


Busdir <= NOT ((a7 AND a6 AND a5 AND NOT IORQ AND NOT RD AND a4 AND a3 AND a2));


d0_I <= ((a1 AND a0 AND ff_bit0)
	OR (a1 AND NOT a0 AND fe_bit0)
	OR (NOT a1 AND a0 AND fd_bit0)
	OR (NOT a1 AND NOT a0 AND fc_bit0));
d0 <= d0_I when d0_OE = '1' else 'Z';
d0_OE <= (a7 AND a6 AND a5 AND NOT IORQ AND NOT RD AND a4 AND a3 AND a2);


d1_I <= ((a1 AND a0 AND ff_bit1)
	OR (a1 AND NOT a0 AND fe_bit1)
	OR (NOT a1 AND a0 AND fd_bit1)
	OR (NOT a1 AND NOT a0 AND fc_bit1));
d1 <= d1_I when d1_OE = '1' else 'Z';
d1_OE <= (a7 AND a6 AND a5 AND NOT IORQ AND NOT RD AND a4 AND a3 AND a2);


d2_I <= ((a1 AND a0 AND ff_bit2)
	OR (a1 AND NOT a0 AND fe_bit2)
	OR (NOT a1 AND a0 AND fd_bit2)
	OR (NOT a1 AND NOT a0 AND fc_bit2));
d2 <= d2_I when d2_OE = '1' else 'Z';
d2_OE <= (a7 AND a6 AND a5 AND NOT IORQ AND NOT RD AND a4 AND a3 AND a2);


d3_I <= ((a1 AND a0 AND ff_bit3)
	OR (a1 AND NOT a0 AND fe_bit3)
	OR (NOT a1 AND a0 AND fd_bit3)
	OR (NOT a1 AND NOT a0 AND fc_bit3));
d3 <= d3_I when d3_OE = '1' else 'Z';
d3_OE <= (a7 AND a6 AND a5 AND NOT IORQ AND NOT RD AND a4 AND a3 AND a2);


d4_I <= ((a1 AND a0 AND ff_bit4)
	OR (a1 AND NOT a0 AND fe_bit4)
	OR (NOT a1 AND a0 AND fd_bit4)
	OR (NOT a1 AND NOT a0 AND fc_bit4));
d4 <= d4_I when d4_OE = '1' else 'Z';
d4_OE <= (a7 AND a6 AND a5 AND NOT IORQ AND NOT RD AND a4 AND a3 AND a2);

FTCPE_fc_bit0: FTCPE port map (fc_bit0,fc_bit0_T,NOT fc_bit4/fc_bit4_CLKF,'0','0');
fc_bit0_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fc_bit0 AND 
	NOT d0.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fc_bit0 AND 
	d0.PIN));

FTCPE_fc_bit1: FTCPE port map (fc_bit1,fc_bit1_T,NOT fc_bit4/fc_bit4_CLKF,'0','0');
fc_bit1_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fc_bit1 AND 
	NOT d1.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fc_bit1 AND 
	d1.PIN));

FTCPE_fc_bit2: FTCPE port map (fc_bit2,fc_bit2_T,NOT fc_bit4/fc_bit4_CLKF,'0','0');
fc_bit2_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fc_bit2 AND 
	NOT d2.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fc_bit2 AND 
	d2.PIN));

FTCPE_fc_bit3: FTCPE port map (fc_bit3,fc_bit3_T,NOT fc_bit4/fc_bit4_CLKF,'0','0');
fc_bit3_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fc_bit3 AND 
	NOT d3.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fc_bit3 AND 
	d3.PIN));

FTCPE_fc_bit4: FTCPE port map (fc_bit4,fc_bit4_T,NOT fc_bit4/fc_bit4_CLKF,'0','0');
fc_bit4_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fc_bit4 AND 
	NOT d4.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fc_bit4 AND 
	d4.PIN));


fc_bit4/fc_bit4_CLKF <= (NOT a1 AND NOT a0 AND NOT WR AND NOT IORQ);

FTCPE_fd_bit0: FTCPE port map (fd_bit0,fd_bit0_T,NOT fd_bit4/fd_bit4_CLKF,'0','0');
fd_bit0_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fd_bit0 AND 
	NOT d0.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fd_bit0 AND 
	d0.PIN));

FTCPE_fd_bit1: FTCPE port map (fd_bit1,fd_bit1_T,NOT fd_bit4/fd_bit4_CLKF,'0','0');
fd_bit1_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fd_bit1 AND 
	NOT d1.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fd_bit1 AND 
	d1.PIN));

FTCPE_fd_bit2: FTCPE port map (fd_bit2,fd_bit2_T,NOT fd_bit4/fd_bit4_CLKF,'0','0');
fd_bit2_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fd_bit2 AND 
	NOT d2.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fd_bit2 AND 
	d2.PIN));

FTCPE_fd_bit3: FTCPE port map (fd_bit3,fd_bit3_T,NOT fd_bit4/fd_bit4_CLKF,'0','0');
fd_bit3_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fd_bit3 AND 
	NOT d3.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fd_bit3 AND 
	d3.PIN));

FTCPE_fd_bit4: FTCPE port map (fd_bit4,fd_bit4_T,NOT fd_bit4/fd_bit4_CLKF,'0','0');
fd_bit4_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fd_bit4 AND 
	NOT d4.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fd_bit4 AND 
	d4.PIN));


fd_bit4/fd_bit4_CLKF <= (NOT a1 AND a0 AND NOT WR AND NOT IORQ);

FTCPE_fe_bit0: FTCPE port map (fe_bit0,fe_bit0_T,NOT fe_bit4/fe_bit4_CLKF,'0','0');
fe_bit0_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fe_bit0 AND 
	NOT d0.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fe_bit0 AND 
	d0.PIN));

FTCPE_fe_bit1: FTCPE port map (fe_bit1,fe_bit1_T,NOT fe_bit4/fe_bit4_CLKF,'0','0');
fe_bit1_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fe_bit1 AND 
	NOT d1.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fe_bit1 AND 
	d1.PIN));

FTCPE_fe_bit2: FTCPE port map (fe_bit2,fe_bit2_T,NOT fe_bit4/fe_bit4_CLKF,'0','0');
fe_bit2_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fe_bit2 AND 
	NOT d2.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fe_bit2 AND 
	d2.PIN));

FTCPE_fe_bit3: FTCPE port map (fe_bit3,fe_bit3_T,NOT fe_bit4/fe_bit4_CLKF,'0','0');
fe_bit3_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fe_bit3 AND 
	NOT d3.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fe_bit3 AND 
	d3.PIN));

FTCPE_fe_bit4: FTCPE port map (fe_bit4,fe_bit4_T,NOT fe_bit4/fe_bit4_CLKF,'0','0');
fe_bit4_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND fe_bit4 AND 
	NOT d4.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT fe_bit4 AND 
	d4.PIN));


fe_bit4/fe_bit4_CLKF <= (a1 AND NOT a0 AND NOT WR AND NOT IORQ);

FTCPE_ff_bit0: FTCPE port map (ff_bit0,ff_bit0_T,NOT ff_bit4/ff_bit4_CLKF,'0','0');
ff_bit0_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND ff_bit0 AND 
	NOT d0.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT ff_bit0 AND 
	d0.PIN));

FTCPE_ff_bit1: FTCPE port map (ff_bit1,ff_bit1_T,NOT ff_bit4/ff_bit4_CLKF,'0','0');
ff_bit1_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND ff_bit1 AND 
	NOT d1.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT ff_bit1 AND 
	d1.PIN));

FTCPE_ff_bit2: FTCPE port map (ff_bit2,ff_bit2_T,NOT ff_bit4/ff_bit4_CLKF,'0','0');
ff_bit2_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND ff_bit2 AND 
	NOT d2.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT ff_bit2 AND 
	d2.PIN));

FTCPE_ff_bit3: FTCPE port map (ff_bit3,ff_bit3_T,NOT ff_bit4/ff_bit4_CLKF,'0','0');
ff_bit3_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND ff_bit3 AND 
	NOT d3.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT ff_bit3 AND 
	d3.PIN));

FTCPE_ff_bit4: FTCPE port map (ff_bit4,ff_bit4_T,NOT ff_bit4/ff_bit4_CLKF,'0','0');
ff_bit4_T <= ((a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND ff_bit4 AND 
	NOT d4.PIN)
	OR (a7 AND a6 AND a5 AND a4 AND a3 AND a2 AND NOT ff_bit4 AND 
	d4.PIN));


ff_bit4/ff_bit4_CLKF <= (a1 AND a0 AND NOT WR AND NOT IORQ);


ma14 <= ((fc_bit0 AND NOT a14 AND NOT a15)
	OR (fd_bit0 AND a14 AND NOT a15)
	OR (fe_bit0 AND NOT a14 AND a15)
	OR (ff_bit0 AND a14 AND a15));


ma15 <= ((fc_bit1 AND NOT a14 AND NOT a15)
	OR (fd_bit1 AND a14 AND NOT a15)
	OR (fe_bit1 AND NOT a14 AND a15)
	OR (ff_bit1 AND a14 AND a15));


ma16 <= ((fc_bit2 AND NOT a14 AND NOT a15)
	OR (fd_bit2 AND a14 AND NOT a15)
	OR (fe_bit2 AND NOT a14 AND a15)
	OR (ff_bit2 AND a14 AND a15));


ma17 <= ((fc_bit3 AND NOT a14 AND NOT a15)
	OR (fd_bit3 AND a14 AND NOT a15)
	OR (fe_bit3 AND NOT a14 AND a15)
	OR (ff_bit3 AND a14 AND a15));


ma18 <= ((fc_bit4 AND NOT a14 AND NOT a15)
	OR (fd_bit4 AND a14 AND NOT a15)
	OR (fe_bit4 AND NOT a14 AND a15)
	OR (ff_bit4 AND a14 AND a15));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9536-7-VQ44


   --------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 \
 | 1                             33 | 
 | 2                             32 | 
 | 3                             31 | 
 | 4                             30 | 
 | 5          XC9536-7-VQ44      29 | 
 | 6                             28 | 
 | 7                             27 | 
 | 8                             26 | 
 | 9                             25 | 
 | 10                            24 | 
 | 11                            23 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              23 a2                            
  2 ma17                             24 TDO                           
  3 ma18                             25 GND                           
  4 GND                              26 VCC                           
  5 Busdir                           27 a3                            
  6 a14                              28 TIE                           
  7 a15                              29 a4                            
  8 RD                               30 TIE                           
  9 TDI                              31 TIE                           
 10 TMS                              32 a5                            
 11 TCK                              33 TIE                           
 12 d4                               34 TIE                           
 13 d3                               35 VCC                           
 14 d2                               36 TIE                           
 15 VCC                              37 a6                            
 16 d1                               38 a7                            
 17 GND                              39 WR                            
 18 d0                               40 ma14                          
 19 TIE                              41 ma15                          
 20 IORQ                             42 ma16                          
 21 a0                               43 TIE                           
 22 a1                               44 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9536-7-VQ44
Optimization Method                         : DENSITY
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : ON
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : LOW
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : OFF
Input Limit                                 : 36
Pterm Limit                                 : 90
