
MSX SRAM memory mapper 512 KB
-----------------------------

This project was done to test a CPLD design on real MSX homecomputer hardware. It implements an MSX memory mapper using just 2 IC's. The CPLD (Complex Programmable Logic Device) generates expanded address lines MA14~MA18 (5 bits = 32 memory mapper blocks of 16 KB each), for use by a 512K x 8 static RAM. Other connections for the SRAM:

MSX cartridge slot #SLTSL -> #ChipEnable
 "       "     "   #RD    -> #OutputEnable
 "       "     "   #WR    -> #Write

Usually #SLTSL is ORed with #MREQ, this was tested but no difference in function or reliability could be found. #MREQ is (normally?) included in #SLTSL signals, but externally combining these signals may affect timing - for better or worse.

Implementation / testing
------------------------

Design was done using schematic entry with Xilinx ISE WebPACK 12.1 on Debian GNU/Linux, synthesized and implemented in a Xilinx XC9536-7C-VQ44 (pin functions are in the file "Fitter report.txt"). The memory mapper supports read-back of the mapper registers. Correct function was verified in hardware on the following MSX models:

* Philips VG8020/20.
* Sony HB-75P.
* Spectravideo SVI 728 (due to its single cartridge slot, only a crude BASIC test program was run on this machine).
* Philips NMS8250/00.
* Gouda slotexpander v5.0 in this NMS8250 (AFAIK this slotexpander is based on / same design as slotexpander by Digital KC, as published in some MSX magazine).
* Sony HB-F9P.
* Sony HB-F1 II.
* Sanyo Wavy PHC-70FD2, on 3.58 and 8 MHz.
* 1chipMSX with original firmware, on 3.58 MHz and its turbo setting.
* 1chipMSX with MSX2+ firmware v3.1 by KdL, again on 3.58 MHz and max speed setting.

An SD card was prepared with a set of test programs & games, and (as far as possible), each program was run on each of the above MSX models. Used software includes:

* MCM's MSXMEM by Armand Simonis (shows slot configuration & mapper size).
* Mem-map v1.02 by D.I.E. (detects number & size of memory mappers).
* MapTest 3.00 by K. Folst.
* TestMap v4.2 by Maarten Verheijdt & Digital KC.
* A crude BASIC program that tests mapper registers & block switching.
* Some simple MSX1 games (but each time, making *sure* the 512 KB mapper is in use before starting the game).
* Some MegaROM disk versions, including one that needs at least 256 KB to run.
* MSX-DOS 2.31.

With most games at least 1 level was played, to verify there are no stability issues when using the mapper for extended periods of time.

Detailed circuit description
----------------------------

The FDCE elements (flip-flop with clock enable and asynchronous clear) were used because they have efficient implementation in XC9500 family devices, and enable parallel decoding of A2~A7 and #IORQ/#WR/A0/A1. This serves to minimize the required data hold time after #IORQ or #WR returns high (data is clocked at low-to-high transition of #IORQ or #WR, whichever comes first), which should help with faster (8, 10 or even 20 MHz) Z80 versions. Single NAND gates to decode #IORQ/#WR/A0/A1 also targets this goal. Each horizontal row of flip-flops represents a single mapper bit for all 4 registers FC~FFh, each vertical row represents all bits for a specific mapper register. For each row there are 2 multiplexers: one to select the bit that is returned when an I/O port FC~FFh is read (this goes back on the databus through a tri-state buffer), and one to select the bit that serves as expanded address line (this goes to a dedicated I/O pin). This setup gives a good balance between speed and required CPLD resources. For the curious: with discrete 74xxx logic, the same function would require at least 6 IC's (+ their interconnections!).
Macrocell power setting was set to "low" because the logic is more than fast enough, and this setting significantly affects (reduces) the CPLD's power consumption. Output slew rates were set to "fast", this may be changed to reduce switching noise (at the cost of increased signal delays).

This design should be easy to modify into a larger memory mapper (6~8 bits for 1/2/4 MB), or remove sections when a smaller one (64/128/256 KB) is needed. Power-up register values were set to match MSX defaults (A0/A1 when reading/writing through Z80 databus, A14/A15 for selecting the expanded addresses to output):

Register:   controls:               A15/A1 A14/A0   power-up value = bit4 bit3 bit2 bit1 bit0
  FCh      0000-3FFFh (page 0)        0      0            3           0    0    0    1    1
  FDh      4000-7FFFh   "   1         0      1            2           0    0    0    1    0
  FEh      8000-BFFFh   "   2         1      0            1           0    0    0    0    1
  FFh      C000-FFFFh   "   3         1      1            0           0    0    0    0    0

It *may* be possible to program the .jed configuration file directly into a PLCC part, if so pinouts will be different since PLCC and VQFP housings have different pin numbering. It probably *will not* be possible to program the .jed file into an XC9536XL part, due to internal differences in these device families. If that is what you want: open a new project in Xilinx ISE WebPACK, starting with the sources provided here.

Practical issues
----------------

For the SRAM, as long as <any address line> goes to <any free SRAM address input>, and <any data line> connects to <any free SRAM data I/O pin>, it makes no difference in function.

On the CPLD the same is true for A2~A7 inputs, D0~D4 signals and expanded address outputs MA14~MA18. But control signals, A0/A1 and A14/A15 should be connected as indicated.

Great care **MUST BE TAKEN** with power supply decoupling and circuit board layout (especially supply connections). I cannot stress this enough - direct quote from a Xilinx user guide: "The minimum decoupling recommendations for CPLD devices are to provide both 0.1 and 0.01 uF capacitors at every Vcc point of the chip and attach them directly to the nearest ground". Note the "minimum" in there, and these guys know what they're talking about!
Also 100 Ohm series resistors were included between SRAM/CPLD outputs (D0~D7 and #BUSDIR) and MSX cartridge slot, to solve problems with fast switching CPLD (and SRAM?) outputs and long signal lines on MSX computer mainboards. Current version uses the BS62LV4006PIP55 from Brilliance Semiconductor, but any common (low power) 5V supply, 512K x 8 SRAM should work. Also used/tested during development: Nec D431000ACZ-70LL and Mitsubishi M5M51008FP-10LL (128K x 8).

Some pictures of what the prototype looks like, can be found in directory "Photos". Note that there is a decoupling capacitor under the SRAM (between SRAM and circuit board), and *several* SMD capacitors directly under the CPLD (100 nF ceramic), which are not visible in the pictures. This may seem overkill, but trust me: it is not. Leave out decoupling capacitors at your own risk! Larger buffer capacitors (like the yellow and blue tantalums I used) are less critical, but still recommended.
In the XC9536 device, the 512 KB mapper uses almost all CPLD resources. This results in severe limitations on which I/O pins can be used for which signals. For this reason, I first let the WebPACK software choose the pin designations, to get a global view of which pins would carry which signals. Then I chose pin designations myself, making small changes to suit placing the CPLD under the SRAM (on underside of the circuit board). Thus keeping wire lengths to a minimum.
A plain ROM cartridge was used as 'donor' for the prototype - Sony's "Creative Greetings" in this case. To make room for the CPLD on the underside of the circuit board, the back of the cartridge housing was modified using a soldering iron (with tip removed). In principle any cartridge could be used, but some cartridges are better suited due to internal space & component placement. Many cartridges only have pins on their connector for signals that are actually used. Therefore I picked a cartridge with a 'fully equipped' edge connector, to make sure any required signal would be available on the inside.


Alwin Henseler

19 August 2011                  http://bitcycle.org

