initialisatie en gebruik PCPWM peripheral PIC

	
;***********************************************************
;Initialize PCPWM
;	NOTES:
; 	1)	PTPER has 12-bit resolution, 4 LSBs of PTPERH and 8 bits of PTPERL
; 	2)	In edge aligned mode, PTMR reset to zero on match with PTPER
;	3)	PDC has 14-bit resolution, 6 LSBs of PDCxH and 8 bits of PDCxL
;	4)	Lower 2 bits of PDC compared to Q clocks
;
;	5)	Resolution(of duty cycle)= log((Fosc/4)/Fpwm)/log(2) = log(5Mhz/20kHz)/log(2) = 8 bits
;		so 6 LSBs of PDCxH and 2 MSBs of PDCxL will be used.
;	   (for 16kHz, resolution = log(5Mhz/16kHz)/log(2) = 8 bits, also.)
;
;*******************************************************************************
INIT_PCPWM

	movlw	b'00000000'			; PTCON0 is configured such that:
	movwf	PTCON0		    	; a) Postscale value is 1:1
								; b) PWM time base input is Fosc/4
								; c) PWM time base mode is free-running for edge-aligned operation
	
;	movlw	0xF9				; PTPERL and PTPERH are set up for a 20KHz PWM frequency.		
;	movwf	PTPERL			    ; 	PTPERH:PTPERL = ((Fosc/4)/(PWMfreq x PTMRps))-1
;	movlw	0x00				; 	PTPERH:PTPERL = ((20MHz/4)/(20KHz x 1))-1 = 249d = F9h
;	movwf	PTPERH			

	movlw	0x37				; PTPERL and PTPERH are set up for a 16KHz PWM frequency.		
	movwf	PTPERL			    ; 	PTPERH:PTPERL = ((Fosc/4)/(PWMfreq x PTMRps))-1
    movlw	0x01				; 	PTPERH:PTPERL = ((20MHz/4)/(16KHz x 1))-1 = 311d = 137h
	movwf	PTPERH	
	
;	movlw	0xF9				; PTPERL and PTPERH are set up for a 3 kHz PWM frequency.		
;	movwf	PTPERL		    	; PTPERH:PTPERL = ((Fosc/4)/(PWMfreq x PTMRps))-1
;	movlw	0x06				; PTPERH:PTPERL = ((20MHz/4)/(20KHz x 1))-1 = 249d = F9h
;	movwf	PTPERH	
	
	movlw	b'01000000'			; PWMCON0 is configured such that:
	movwf	PWMCON0			; a) PWM0, PWM1, PWM2, PWM3, PWM4, and PWM5 are enabled for output.
								; b) All PWM I/O pairs are set to complimentary mode
										
	movlw	b'00000001'			;PWMCON1 is configured such that:
	movwf	PWMCON1				; a) Special event trigger post-scaler is set to 1:1
								; b) Special event trigger occurs when time-base is counting upwards
								; c) Updates from duty cycle and period buffer registers are enabled.
								; d) Output overrides via OVDCON are synchronous to the PWM timebase.			


;	movlw	b'00001010'			;1us deadtime instead of 2us		
;	movlw	b'00010100'			;DTCON is configured such that:
	movlw	b'00011100'          ; 3.2 us
	movwf	DTCON				; a) Clock source for dead-time is Fosc/2.
								; b) Dead time = Dead time value / (Fosc/2) = 2uS.							
;	clrf	DTCON				;DTCON for zero dead-time (relying on IRAMS cross-conduction prevention logic)							

;	movlw	b'00000000'
	movlw	b'11111111'			;OVDCOND is configured such that there is no output override.
	movwf	OVDCOND
	
	movlw	b'00000000'			;OVDCONS is configured such that all PWM outputs are 0 upon power-up.
;	movlw	b'11111111'			;OVDCONS is configured such that all PWM outputs are 1 (inactive) upon power-up.
	movwf	OVDCONS
	
	
	;FLTA is overcurrent fault, muxed via configuration bit to RC1
	;FLTB is overvoltage fault on RC2
;	bsf		TRISC, 1			;Ensure that RC1 is an input
;	bsf		TRISC, 2			;Ensure that RC2 is an input
;	movlw	b'10000000'			;Fault A and FaultB are disabled.
;	movlw	b'10000011'			;Fault B is disabled
;	movlw	b'10010001'			;Fault A and FaultB are enabled in catastrophic mode.
;	movlw	b'10110011'			;FLTCONFIG is configured such that: 
	movlw	b'00000000'			;Fault disabled.
	movwf	FLTCONFIG			; a) Enable fault condition on break-point for use with ICD2
								; b) Enable FaultA in cycle-by-cycle mode
								; c) Enable FaultB in cycle-by-cycle mode
								; d) Fault A and Fault B disable PWM channels 0 to 5
	
	movlw	0x00				;SEVTCMPL and SEVTCMPH are clear.
	movwf	SEVTCMPL
	movlw	0x00
	movwf	SEVTCMPH

	clrf	PDC0L				;PDC0L, PDC1L, PDC2L, PDC3L, PDC0H, PDC1H, PDC2H, PDC3H 
	clrf	PDC1L				; 	are clear so that duty cycles are initially 0.
	clrf	PDC2L	
	clrf	PDC3L	
	clrf	PDC0H	
	clrf	PDC1H	
	clrf	PDC2H	
	clrf	PDC3H	

	bsf		PTCON1, PTEN		;PTEN bit in the PTCON1 is set to enable the PWM time base.
	
	return