Fuses 18F2320

; [START OF CONFIGURATION BITS]
;
;  The following is an assignment of address values for all of the
;  configuration registers for the purpose of table reads and writes,
;  and for programming configuration words.

CONFIG1H       EQU    H'300001'
CONFIG2L       EQU    H'300002'
CONFIG2H       EQU    H'300003'
CONFIG3H       EQU    H'300005'
CONFIG4L       EQU    H'300006'
CONFIG5L       EQU    H'300008'
CONFIG5H       EQU    H'300009'
CONFIG6L       EQU    H'30000A'
CONFIG6H       EQU    H'30000B'
CONFIG7L       EQU    H'30000C'
CONFIG7H       EQU    H'30000D'

;Configuration Byte 1H Options
IESO_ON_1       EQU  H'FF' ; Internal External Oscillator Switch Over mode enabled
IESO_OFF_1      EQU  H'7F' ; Internal External Oscillator Switch Over mode disabled
FSCMEN_ON_1     EQU  H'FF' ; Fail Safe Clock Monitor enabled
FSCMEN_OFF_1    EQU  H'BF' ; Fail Safe Clock Monitor disabled
RC_OSC_1        EQU  H'FF' ; External RC on OSC1, OSC2 as Fosc/4
RCIO_OSC_1      EQU  H'F7' ; External RC on OSC1, OSC2 as RA6
LP_OSC_1        EQU  H'F0' ; LP Oscillator
XT_OSC_1        EQU  H'F1' ; XT Oscillator
HS_OSC_1        EQU  H'F2' ; HS Oscillator
HSPLL_OSC_1     EQU  H'F6' ; HS + PLL
EC_OSC_1        EQU  H'F4' ; External Clock on OSC1, OSC2 as Fosc/4
ECIO_OSC_1      EQU  H'F5' ; External Clock on OSC1, OSC2 as RA6
INTIO1_OSC_1    EQU  H'F9' ; Internal RC, OSC1 as RA7, OSC2 as Fosc/4
INTIO2_OSC_1    EQU  H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6

RCIO6_OSC_1     EQU  H'F7' ; compatabilty - RCIO new - BD 9/27/02
ECIO6_OSC_1     EQU  H'F5' ; compatabilty - ECIO new - BD 9/27/02
INTIO7_OSC_1    EQU  H'F9' ; compatabilty - INTIO1 new - BD 9/27/02
INTIO67_OSC_1   EQU  H'F8' ; compatabilty - INTIO2 new - BD 9/27/02

;Configuration Byte 2L Options
BORV_20_2       EQU  H'FF' ; BOR Voltage - 2.0v
BORV_27_2       EQU  H'FB' ;               2.7v
BORV_42_2       EQU  H'F7' ;               4.2v
BORV_45_2       EQU  H'F3' ;               4.5v
BOR_ON_2        EQU  H'FF' ; Brown-Out Reset enabled
BOR_OFF_2       EQU  H'FD' ; Brown-Out Reset disabled
PWRT_OFF_2      EQU  H'FF' ; Power-Up Timer disabled
PWRT_ON_2       EQU  H'FE' ; Power-Up Timer enabled

;Configuration Byte 2H Options
WDT_ON_2        EQU  H'FF' ; Watch Dog Timer enabled
WDT_OFF_2       EQU  H'FE' ; Watch Dog Timer disabled
WDTPS_32K_2     EQU  H'FF' ;   1:32,768    WDT Postscaler ratio
WDTPS_16K_2     EQU  H'FD' ;   1:16,384
WDTPS_8K_2      EQU  H'FB' ;   1: 8,192
WDTPS_4K_2      EQU  H'F9' ;   1: 4,096
WDTPS_2K_2      EQU  H'F7' ;   1: 2,048
WDTPS_1K_2      EQU  H'F5' ;   1: 1,024
WDTPS_512_2     EQU  H'F3' ;   1:   512
WDTPS_256_2     EQU  H'F1' ;   1:   256
WDTPS_128_2     EQU  H'EF' ;   1:   128
WDTPS_64_2      EQU  H'ED' ;   1:    64
WDTPS_32_2      EQU  H'EB' ;   1:    32
WDTPS_16_2      EQU  H'E9' ;   1:    16
WDTPS_8_2       EQU  H'E7' ;   1:     8
WDTPS_4_2       EQU  H'E5' ;   1:     4
WDTPS_2_2       EQU  H'E3' ;   1:     2
WDTPS_1_2       EQU  H'E1' ;   1:     1

;Configuration Byte 3L Options
MCLRE_ON_3      EQU  H'FF' ; MCLR enabled, RE3 input disabled
MCLRE_OFF_3     EQU  H'7F' ; MCLR disabled, RE3 input enabled
PBAD_ANA_3      EQU  H'FF' ; PORTB<4:0> pins reset as analog pins
PBAD_DIG_3      EQU  H'FD' ; PORTB<4:0> pins reset as digital pins   incorrect bit was cleared - BD 5/30/2002
CCP2MX_ON_3     EQU  H'FF' ; CCP2 pin function on RC1
CCP2MX_OFF_3    EQU  H'FE' ; CCP2 pin function on RB3
CCP2MX_C1_3     EQU  H'FF' ; CCP2 pin function on RC1 (alt defn)
CCP2MX_B3_3     EQU  H'FE' ; CCP2 pin function on RB3 (alt defn)

;Configuration Byte 4L Options
DEBUG_ON_4      EQU  H'7F' ; BacKground deBUGger enabled
DEBUG_OFF_4     EQU  H'FF' ; BacKground deBUGger disabled
LVP_ON_4        EQU  H'FF' ; Low Voltage Prgramming enabled
LVP_OFF_4       EQU  H'FB' ; Low Voltage Prgramming disabled
STVR_ON_4       EQU  H'FF' ; Stack over/underflow Reset enabled
STVR_OFF_4      EQU  H'FE' ; Stack over/underflow Reset disabled

BKBUG_ON_4      EQU  H'7F' ; compatabilty - DEBUG new - BD 9/27/02
BKBUG_OFF_4     EQU  H'FF' ; compatabilty - DEBUG new - BD 9/27/02

;Configuration Byte 5L Options
; Protect program memory blocks from programmer reads and writes (see Config Byte 6L)
CP0_ON_5        EQU  H'FE' ; Block 0 protected
CP0_OFF_5       EQU  H'FF' ; Block 0 readable/ may be writable 
CP1_ON_5        EQU  H'FD' ; Block 1 protected
CP1_OFF_5       EQU  H'FF' ; Block 1 readable/ may be writable
CP2_ON_5        EQU  H'FB' ; Block 2 protected
CP2_OFF_5       EQU  H'FF' ; Block 2 readable/ may be writable
CP3_ON_5        EQU  H'F7' ; Block 3 protected
CP3_OFF_5       EQU  H'FF' ; Block 3 readable/ may be writable


;Configuration Byte 5H Options
;  Protect blocks from programmer reads and writes (see Config Byte 6H)
CPB_ON_5H       EQU  H'BF' ; Boot Block protected
CPB_OFF_5       EQU  H'FF' ; Boot Block readable / may be writable 
CPD_ON_5        EQU  H'7F' ; Data EE memory protected
CPD_OFF_5       EQU  H'FF' ; Data EE memory readable / may be writable

;Configuration Byte 6L Options
;  Protect program memory blocks from table writes and programmer writes
WRT0_ON_6       EQU  H'FE' ; Block 0 write protected
WRT0_OFF_6      EQU  H'FF' ; Block 0 writable
WRT1_ON_6       EQU  H'FD' ; Block 1 write protected
WRT1_OFF_6      EQU  H'FF' ; Block 1 writable
WRT2_ON_6       EQU  H'FB' ; Block 2 write protected
WRT2_OFF_6      EQU  H'FF' ; Block 2 writable
WRT3_ON_6       EQU  H'F7' ; Block 3 write protected
WRT3_OFF_6      EQU  H'FF' ; Block 3 writable

;Configuration Byte 6H Options
;  Protect blocks from table writes and programmer writes
WRTC_ON_6       EQU  H'DF' ; Config registers write protected
WRTC_OFF_6      EQU  H'FF' ; Config registers writable
WRTB_ON_6       EQU  H'BF' ; Boot block write protected
WRTB_OFF_6      EQU  H'FF' ; Boot block writable
WRTD_ON_6       EQU  H'7F' ; Data EE write protected
WRTD_OFF_6      EQU  H'FF' ; Data EE writable 

;Configuration Byte 7L Options
;  Protect program memory blocks from table reads executed from other blocks
EBTR0_ON_7      EQU  H'FE' ; Block 0 protected 
EBTR0_OFF_7     EQU  H'FF' ; Block 0 readable
EBTR1_ON_7      EQU  H'FD' ; Block 1 protected
EBTR1_OFF_7     EQU  H'FF' ; Block 1 readable
EBTR2_ON_7      EQU  H'FB' ; Block 2 protected
EBTR2_OFF_7     EQU  H'FF' ; Block 2 readable
EBTR3_ON_7      EQU  H'F7' ; Block 3 protected
EBTR3_OFF_7     EQU  H'FF' ; Block 3 readable

;Configuration Byte 7H Options
;  Protect block from table reads executed in other blocks
_EBTRB_ON_7H      EQU  H'BF' ; Boot block read protected
_EBTRB_OFF_7H     EQU  H'FF' ; Boot block readable

;=======================================================================
;
;   Device ID registers
;
;  The following is an assignment of address values for the Device ID
;  registers for the purpose of table reads.

DEVID1         EQU    H'3FFFFE'
DEVID2         EQU    H'3FFFFF'

	ifndef CONFIG_REQ
		ifdef PLL@REQ									; Do we require the PLL ?
			__CONFIG CONFIG1, HSPLL_OSC_1	
		else
			__CONFIG CONFIG1H, HS_OSC_1
        endif
        __CONFIG CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2
        ifdef WATCHDOG_REQ
        	__CONFIG CONFIG2H, WDT_ON_2 & WDTPS_128_2
        else
        	__CONFIG CONFIG2H, WDT_OFF_2 & WDTPS_128_2
        endif
        __CONFIG CONFIG3H, MCLRE_ON_3
        ifdef DEBUG@REQ									; Do we require DEBUG ?
        	__CONFIG CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_ON_4
        else
        	__CONFIG CONFIG4L, STVR_ON_4 & LVP_OFF_4 & DEBUG_OFF_4
		endif
	endif 
        LIST

DEVICE 18F2320                

@CONFIG_REQ
@__CONFIG CONFIG1H, HS_OSC_1                              ;ik maak gebruik van de interne oscillator
@__CONFIG CONFIG2L, BOR_ON_2 & BORV_20_2 & PWRT_ON_2
@__CONFIG CONFIG2H, WDT_OFF_2
@__CONFIG CONFIG3H, MCLRE_OFF_3 & CCP2MX_ON_3
@__CONFIG CONFIG4L, LVP_OFF_4

ALL_DIGITAL TRUE             
    

;        76543210
TRISB = %11101111       ; B4 als output      

CLEAR                        

WHILE 1=1

HIGH PORTB.4

DELAYMS 5000

LOW PORTB.4

DELAYMS 1000

WEND

END

Error:
Verify error at adress: 0x300000. Value in image is 0xFF and value in target is 0x00.